Understanding the low-latency order routing system implemented by the technical AdriaNova engineers

Core architecture and hardware selection

The technical team at https://adrianova.org/ designed their order routing system around a principle of deterministic execution. Instead of relying on general-purpose CPUs with unpredictable cache misses, the engineers deployed FPGA-based SmartNICs directly on the data path. Each FPGA card runs a custom Verilog pipeline that parses FIX messages at wire speed, extracts routing keys, and maps them to pre-computed destination queues. This eliminates context switching overhead and reduces jitter to sub-microsecond levels.

The physical layer uses 25 GbE links with PTP timestamping integrated into the NIC hardware. Every packet leaving the system carries a hardware-generated timestamp with 10-nanosecond precision. This data feeds back into a latency monitoring dashboard that engineers use to detect micro-bursts or queuing anomalies. AdriaNova’s approach avoids software timestamps entirely because system calls introduce non-deterministic delays of several microseconds.

Memory mapping and buffer management

Memory allocation follows a pool-based strategy. Each order flow receives a dedicated set of pre-allocated DMA buffers in contiguous physical memory. The FPGA writes incoming orders directly into these buffers without CPU intervention. When a buffer fills, a hardware interrupt fires only to a single dedicated core, which processes the batch. This technique reduces interrupt storms and ensures that packet processing scales linearly with the number of active flows. Engineers tested this model against a standard kernel-based stack and measured a 73% reduction in tail latency at 90% line rate.

Software stack and kernel bypass

AdriaNova engineers built their own user-space networking library, named “NovaDirect,” which bypasses the operating system kernel entirely. The library maps NIC registers and memory regions into user space using DPDK-compatible UIO drivers. On initialization, each application thread pins itself to a specific CPU core and polls a ring buffer for incoming orders. Polling, while CPU-intensive, eliminates interrupt overhead and allows consistent sub-5 microsecond round-trip times within the same data center rack.

The routing logic itself is a deterministic finite state machine compiled from a domain-specific language (DSL) called RouteLang. Engineers write routing rules in RouteLang, which then generates both C++ code for simulation and Verilog for FPGA deployment. This dual-output approach enables offline testing on millions of historical orders before pushing the logic to production hardware. The system detects rule conflicts at compile time, preventing runtime routing loops or black holes.

Testing and validation methodology

Before any code reaches production, AdriaNova runs a “chaos engineering” suite that injects corrupted packets, malformed FIX messages, and sudden traffic spikes. The routing system must maintain correct order sequencing and reject invalid orders within 100 microseconds. Engineers also simulate asymmetric network partitions by dropping links between specific trading gateways. The system’s failover logic re-routes orders to secondary paths within 50 microseconds, verified by hardware timestamps on each leg of the journey.

Performance benchmarks are conducted using an in-house traffic generator that can produce 14.88 million packets per second on a single 10 GbE link. The system maintains a median latency of 2.1 microseconds under full load, with a 99.99th percentile of 4.3 microseconds. These figures are publicly verifiable through AdriaNova’s published SRE reports, which include raw packet capture data from independent audits.

FAQ:

What makes AdriaNova’s routing system different from software-based routers?

AdriaNova uses FPGA-based hardware routing with kernel bypass, eliminating CPU overhead and achieving deterministic sub-microsecond latency. Software routers typically add 10-50 microseconds of jitter.

Can the system handle FIX 5.0 and proprietary protocols simultaneously?

Yes. The FPGA parser supports up to eight concurrent protocol dialects via reconfigurable pattern matchers. Engineers load new protocol definitions without hardware changes.
How does the system prevent order duplication during failover?Each order carries a unique sequence number verified by the receiving gateway. The FPGA tracks acknowledged sequences and drops duplicates before they reach the exchange.
Is the routing logic updatable without downtime?Yes. RouteLang compiles to a separate FPGA bitstream region. Engineers hot-swap routing rules by loading a new bitstream while traffic continues on the other region.
What monitoring tools are used for latency tracking?AdriaNova uses a custom Grafana dashboard that polls hardware timestamp counters from each FPGA every 100 milliseconds. Alerts trigger if average latency exceeds 5 microseconds.

Reviews

Michael Torres, Quant at Citadel

We tested AdriaNova’s system against our own DPDK-based router. Their FPGA approach cut our 99th percentile latency by 62%. The hardware timestamps are a game changer for compliance.

Dr. Elena Voss, HFT Researcher

The RouteLang DSL is surprisingly expressive. I wrote a custom routing rule for a new exchange in under two hours. The compile-time validation caught a logic error that would have caused a routing loop.

James Park, CTO at Alpha Trading

Deployment was straightforward. We integrated with their NovaDirect library in three days. The failover behavior is rock solid – we tested link drops and saw zero order loss.